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keypad decoder and i/o expansion data sheet adp5585 rev. c document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may res ult from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. o ne technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2011 C 2013 analog devices, inc. all rights reserved. technical support www.analog.com feature s 16- element fifo for event recording 10 configurable i/os allowing functions such as key pad decoding for a matrix of up to 5 5 11 gpio s ( 5 6 ) with adp5585acxz - 01- r7 models key press/release interrupts gpio functions gpi with selectable interru pt level 100 k or 300 k pull - up resistors 300 k pull - down resistors gpo with push - pull or open - drain programmable logic bl ock pwm generator internal pwm g eneration external pwm with internal pwm and function reset generator s i 2 c interface with f ast mode plus (fm+) s upport of up to 1 mhz open - drain interrupt output 16- b all wlcsp , 1.59 mm 1.59 mm 16- lead lfcsp, 3 mm 3 mm applications k eypad entrie s and input/output expansion capabilities smart phones, r emote controls, and came ras healthcare, industrial, and instru mentation functional block dia gram sda gpi scan and decode uvlo por i 2 c interface oscillator registers key scan and decode logic i/o config int rst/r5 pwm scl vdd adp5585 gnd reset1 gen reset2 gen 09841-001 r0 r3 r1 r2 r4 c0 c1 c2 c3 c4 figure 1. general description the adp5585 is a 10 input/output port expander with a built i n keyp ad matrix decoder, programmable logic, reset generator, and pwm generator. i nput/output expand er ics are used in portable devices (phones, remote controls, and cameras) and non portable applications (healthcare, industrial , and instrumen tation). i/o expanders can be used to increase the number of i/os available to a proces sor or to reduce the number of i/os required through interface connectors for front panel designs. the adp5585 handles all key scanning and decoding and can flag the main processor via an interrupt line that new key events have occurred. gpi changes and logic changes can also be tra cked as events via the fifo, eliminating the need to monitor different registers for event changes. the adp5585 is equipped with a fifo to store up to 16 events. events can be read back by the processor via an i 2 c - c ompatible interface. the adp5585 frees up the main processor from having to monitor the keypad, thereby reducing power consumption and/or increasing processor bandwidth for performing other functions. the programmable logic functions allow common logic require - ments t o be integrated as part of th e gpio expander , thus saving board area and cost.
adp5585 data sheet rev. c | page 2 of 40 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 timing diagram ........................................................................... 4 absolute maximum ratings ............................................................ 5 thermal resistance ...................................................................... 5 esd caution .................................................................................. 5 pin configurations and function descriptions ........................... 6 theory of operation ........................................................................ 7 device enable ................................................................................ 8 device overview .......................................................................... 8 functional description .....................................................................9 event fifo .....................................................................................9 key scan control ...........................................................................9 gpi input ..................................................................................... 12 gpo output ................................................................................ 12 logic blocks ................................................................................ 12 pwm block ................................................................................. 13 reset blocks ................................................................................ 14 register interface ............................................................................ 15 reg ister map ................................................................................... 17 detailed register descriptions ................................................. 19 applications diagram .................................................................... 36 outline dimensions ....................................................................... 37 ordering guide .......................................................................... 38 revision history 1 / 13 rev. b to rev. c changes to detailed register description section .................... 19 changes to table 31 and table 32 ................................................ 24 changes to table 33, table 34, and table 35 ............................... 25 changes to table 37 ........................................................................ 26 changes to table 39 ........................................................................ 27 changes to table 41 and table 43 ................................................ 28 changes to table 45 ........................................................................ 29 changes to table 47 ........................................................................ 30 changes to table 64 ........................................................................ 34 changes to figure 27 ...................................................................... 36 7/12 rev. a to r ev b changes to table 5 ............................................................................ 8 updated outline dimensions ....................................................... 36 changes to ordering guide .......................................................... 37 10 /11 rev. sp0 to rev. a added 16 - lead lfcsp_wq package .............................. universal changes to features section ............................................................ 1 added figure 4; renumbered sequentially ................................... 6 changes to table 4 ............................................................................. 6 changes to device enable section and table 5 ............................. 8 change to general section ............................................................ 11 changes to logic blocks section .................................................. 12 changes to pwm block section .................................................. 13 changes to interrupts section ...................................................... 14 changes to register interface section ......................................... 15 changes to figure 27 ...................................................................... 35 updated outline dimensions ....................................................... 36 changes to ordering guide .......................................................... 38 5/11 revision sp 0: initial version
data sheet adp5585 rev. c | page 3 of 40 specifications vdd = 1.8 v to 3.3 v, t a = t j = ? 40 c to + 85 c , unless otherwise noted 1 . table 1 . parameter symbol test conditions/comments min typ max unit supply voltage vdd input voltage range vdd 1.65 3.6 v undervoltage lockout threshold uvlo vdd uvlo active, vdd falling 1.2 1.3 v uvlo inactive, vdd rising 1.4 1.6 v supply current standby current i stnby vdd = 1.65 v 1 4 a vdd = 3.3 v 1 10 a operating current ( one key press) i scan 1 s can = 10 ms, core_freq = 50 khz, scan active, 300 k? pull - up, vdd = 1.65 v 30 40 a i scan2 s can = 10 ms, core_freq = 50 khz, scan active, 100 k? pull - up, vdd = 1.65 v 35 45 a i scan3 s can = 10 ms, core_freq = 50 khz, scan active , 300 k? pull - up, vdd = 3.3 v 75 85 a i scan4 s can = 10 ms, core_freq = 50 khz, s can active , 100 k? pull - up, vdd = 3.3 v 80 90 a pull - up, pull - down resistance pull -up option 1 50 100 150 k? option 2 150 300 450 k? pull - down 150 300 450 k? input logic level ( rst , scl, sda, r0, r1, r2, r3, r4, r5, c0, c1, c2, c3, c4) input voltage logic low v il 0.3 vdd v logic high v ih 0.7 vdd v input leakage current (per pin) v i- leak 0.1 1 a push - pull output logic level (r0, r1, r2, r3, r4, r5, c0, c1, c2, c3, c4) output v oltage logic low v ol1 sink current = 10 ma , maximum of five gpios active simultaneously 0.4 v v ol2 sink current = 10 ma , all gpios active simultaneously 0.5 v logic high v oh source current = 5 ma 0.7 vdd v logic high leakage current (per pin) v oh - leak 0.1 1 a open - drain output logic level ( int , sda) output voltage logic low int v ol3 i sink = 10 ma 0.4 v sda v ol4 i sink = 20 ma 0.4 v logic high leakage current (per pin) v oh - leak 0.1 1 a logic propagation delay 125 300 ns ff hold time 2 0 ns ff setup time 2 175 ns gpio debounce 2 70 s internal oscillator fr equency 3 osc freq 900 1000 1100 khz
adp5585 data sheet rev. c | page 4 of 40 parameter symbol test conditions/comments min typ max unit i 2 c timing specifications delay from uvlo/reset inactive to i 2 c access 60 s scl clock frequency f scl 0 1000 khz scl high time t high 0.26 s scl low time t low 0.5 s data setup time t su; dat 50 ns data hold time t hd; dat 0 s setup time for repeated start t su; sta 0.26 s hold time for start/repeated start t hd; sta 0.26 s bus free time for stop and start condition t buf 0.5 s setup time for stop condition t su; sto 0.26 s data valid time t vd; dat 0.45 s data valid acknowledge t vd; ack 0.45 s rise time for scl and sda t r 120 ns fall time for scl and sda t f 120 ns pulse width of suppressed spike t sp 0 50 ns capacitive load for each bus line c b 4 550 pf 1 all limits at temperature extremes are gua ranteed via correlation using standard stat istical quality control (sqc). typical va lues are at t a = 25c, vdd = 1.8 v. 2 guaranteed by design. 3 all timers are referenced from the base oscillator and have the same 10% accuracy. 4 c b is the total capacitance of one bus line in picofarads. timing diagram sda scl sda scl s sr ps first clock cycle ninth clock ninth clock 1/ f scl 70% 30% 70% 30% 70% 30% 70% 30% 70% 30% 70% 30% 70% 30% t f t f t r t r t high t vd; dat t su; dat t su; sta t hd; dat t hd; sta t vd; ack t sp t su; sto t buf t low t hd; sta v il = 0.3vdd v ih = 0.7vdd 09841-002 figure 2. i 2 c interface timing diagram
data sheet adp5585 rev. c | page 5 of 40 absolute maximum rat ings table 2 . parameter rating vdd to gnd ? 0.3 v to + 4 v scl, sda, rst , int , r0, r1, r2, r3, r4, c0, c1, c2, c3, c4 to gnd ? 0.3 v t o (vdd + 0.3 v) temperature range operating (ambient) ? 40 c to +85 c 1 operating ( junction ) ? 40 c to +125 c storag e ? 65 c to +150 c 1 in applications where high power dissipation and poor thermal resistance are present, the maximum ambient temperature may need to be derated. maximum ambient temperature (t a (max) ) is dependent on the maximum operating junction temper ature (t j (maxop) = 125 c), the maximum power dissipation of the device (p d (max) ), and the junction - to - ambient thermal resistance of the device /package in the application ( ja ), using the following equation: t a (max) = t j (maxop) ? ( ja p d (max) ). str esses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this spe cification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. absolute maximum ratings apply individually only, not in combination. unless otherwise specified, all other voltages are referenc ed to gnd. thermal resistance ja is specified for the worst - case conditions, that is, a device soldered in a printed circuit board (pcb) for surface - mount packages. table 3 . thermal resistance ja unit 16- ball wlcsp 62 c/w max imum power dissipation 70 mw 16 - lead lfcsp 67.154 c/w maximum power dissipation 7 0 mw esd caution
adp5585 data sheet rev. c | page 6 of 40 pin configurations and function descriptions int rst/r5 09841-003 1 a b c d 234 c1 r2 vdd c2 sda r4 c3 r1 scl c4 r0 gnd c0 r3 ball a1 corner top view (ball side down) not to scale 09841-027 12 11 10 1 3 4 vdd rst(r5) c4 9 c3 r4 r2 2 r3 r1 6 c 0 5 r 0 7 c 1 8 c 2 1 6 i n t 1 5 s c l 1 4 s d a 1 3 g n d top view not to scale notes 1. the exposed pad is not connected. it is recommended to connect the exposed pad to ground for thermal dissipation. figure 3. wlcsp pin configuration figure 4. lfcsp pin configuration table 4. pin function descriptions pin no. wlcsp lfcsp mnemonic description d1 1 r4 gpio 5 (gpio alternate function: reset1). th is pin functions as row 4 when used as a keypad. d2 2 r3 gpio 4 (gpio alternate function: logic block input lc, pwm_out). this pin functions as row 3 when used as a keypad. c1 3 r2 gpio 3 (gpio alternate function: logic block input lb ). this pin functions as row 2 when used as a keypad. c2 4 r1 gpio 2 (gpio alternate function: logic block input la). this pin functions as row 1 when used as a keypad. b1 5 r0 gpio 1 (gpio alternate function: logic block output ly ). this pin functions as row 0 when used as a keypad. b4 6 c0 gpio 7. this pin functions as column 0 when used as a keypad. c3 7 c1 gpio 8. this pin functions as column 1 when used as a keypad. c4 8 c2 gpio 9. this pin functions as column 2 when used as a keypad. d3 9 c3 gpio 10 (gpio alternate function: pwm_in). this pin functions as column 3 when used as a keypad. d4 10 c4 gpio 11 (gpio alternate function: reset2). this pin functions as column 4 when used as a keypad. b3 11 rst /r5 input reset signal. to expand the keypad matrix, select the adp5585acbz-01-r7 or the adp5585acpz-01-r7 device model for this pin to function as gpio 6/row 5. a1 12 vdd supply voltage input. a4 13 gnd ground. a2 14 sda i 2 c data input/output. a3 15 scl i 2 c clock input. b2 16 int open-drain interrupt output. ep ep exposed pad. the exposed pad is not connected. it is recommended to connect the exposed pad to ground for thermal dissipation.
data sheet adp5585 rev. c | page 7 of 40 theory of operation row 0 sda i 2 c interface i 2 c busy? oscillator registers logic i/o configuration int rst/r5 row 1 row 2 row 3 row 4 row 5 col 1 col 0 col 2 col 3 col 4 (r0) (r1) (r2) (r3) (r4) (rst/r5) (c0) (c1) (c2) (c3) (c4) (r0) (r1) (r2) (r3) (r1) (r2) (r3) (r0) (r4) (rst/r5) (c0) (c1) (c2) (c3) (c4) gpio 1 la gpio 2 gpio 3 gpio 4 gpio 5 gpio 6 gpio 7 gpio 8 gpio 9 gpio 10 gpio 11 lb lc ly pwm (r3) (c3) pwm_in pwm_out (r4) reset1 (c4) reset2 key event gpi event logic event scl v dd adp5585 gnd r0 r3 r1 r2 r4 c0 c1 c2 c3 c4 rst (r5) 09841-004 reset2 gen reset1 gen gpi scan and decode key scan and decode fifo update uvlo por figure 5. internal block diagram
adp5585 data sheet rev. c | page 8 of 40 device enable when sufficient voltage is applied to vdd and the rst pin is driven with a logic high level, the adp5585 starts up in standby mode with all settings at default. the user can configure the device via the i 2 c interface. when the rst pin is low, the adp5585 enters a reset state and all settings return to default. the rst pin features a debounce filter. if using the adp5585acbz - 01- r7 or adp5585acpz - 01- r7 device model , the rst pin acts as an extra row pin. without a reset pin, t he only method to reset the device is by bringing vdd below the uvlo threshold. device overview the adp5585 contains 10 multi configurable input/output pins . each pin can be programmed to enable the device to carry out its various functions , as follow s: ? keypad matrix decoding ( five - column by five - row matrix max imum ) . ? general - purpose i/o expansion (up to 10 input s /outputs ) . ? pwm generation . ? l ogic function building blocks (up to three inputs and one output) . ? two reset generators . all 10 input/output pins have an i / o st ructure as shown in figure 6 . i/o vdd 100k? debounce 300k? 300k? 09841-005 i/o drive figure 6 . i/o s tructure each i/o can be pulled up with a 100 k or 300 k resistor or pulled down with a 300 k resistor. for logic output driv e, each i/o has a 5 ma pmos source and a 10 ma nmos sink for a push - pull type output. for open - drain output situations, the 5 ma pmos source is not enabled. for logic input applications, e ach i/o can be sampled directly or , alternatively, s ampled through a debounce filter. the i/o structure shown in figure 6 allows for all gpi and gpo functions , as well as pwm and clock divide functions. for key matrix scan and decode, the scanning circuit uses the 100 k or 300 k resistor for pulling up keypad row pins and the 10 ma nmos sinks for grounding keypad column pins (see the key scan control section for details about key decoding). configuration of the device is carrie d out by programming an array of internal registers via the i 2 c interface. feedback of device status and pending interrupts can be flagged to an external processor by using the int pin . the adp5585 is offered with three feature sets . table 5 lists the options that are available for each model of the adp5585. table 5 . matrix options by device model model description adp5585acbz -00-r7 gpio pull up (default option) 5 - r ow 5 - column matrix adp5585acbz -01-r7 row 5 added to gpios 6 - row 5 - column matrix adp5585acbz -02-r7 no pull - up resistors to special function pins 1 5 - row 5 - column matrix adp5585acbz -04-r7 pull - down resistors to all gpio pins on start -up 5 - row 5 - column matrix adp5585acpz -00-r7 gpio pull up (default option) 5 - row 5 - column matrix adp5585acpz -01-r7 row 5 added to gpios 6 - row 5 - column matrix adp5585ac p z -03-r7 alternate i 2 c a ddress (0x30) 5 - row 5 - column matrix 1 special function pins are defined as r0, r3, r4, and c4. see table 4 for details.
data sheet adp5585 rev. c | page 9 of 40 functional descriptio n event fifo before going into detail on the various adp5585 blocks, it is important to understand the function of the event fifo . the adp5585 features an event fifo that can record as many as 16 eve nts. by default, the fifo primarily records key eve nts , such as key press and key release . however , it is possible to configure the general - purpose input (gpi) and logic activity to generate event information on the fifo as well . an event count, ec[4:0] , is composed of five bits and works in tandem with the fif o so that the user knows how much of the fifo must be read back at any given time. the fifo is comp os ed of 16 eight - bit sections that the user accesses by readin g the fifo_x registers. the actual fifo is not in user accessible registers until a read occurs . the fifo can be thought of as a first in first out buffer that is used to fill regis ter 0x03 to register 0x12. the event fifo is made up of 16 eight - bit registers. in each register, bits[ 6 :0 ] hold the event identifier, and bit 7 holds the event stat e. with seven bits, 127 different events can be identified. see table 11 for event decoding. event1[7:0] e ve n t 8_ i d e n t i f i e r[6:0] event2[7:0] event3[7:0] event4[7:0] event13[7:0] event14[7:0] event15[7:0] event16[7:0] event5[7:0] event6[7:0] event7[7:0] event8[7:0] event9[7:0] event10[7:0] event 1 1[7:0] event12[7:0] 7 e ve n t 8_ s t a t e gpi events ec[4:0] ovrflow_int ke y events logic events 6 5 4 3 2 1 0 09841-006 fifo upd a te figure 7 . breakdown of eventx[7:0] bits when events are available on the fifo, the user should f irst read back the event count, ec[4:0], to determine how many events must be read back. events can be read from the top of the fifo only . when an event is read back, all remaining events in the fifo are shifted up one location , and the ec[4:0] count is de cremented. ke y 3 pressed ke y 3 released gpi 7 active ec = 3 ke y 3 released gpi 7 active ec = 2 gpi 7 active ec = 1 ec = 0 09841-007 third read second read first read figure 8 . fifo operation the fifo registers (0x03 to 0x12) always poi nt to the top of the fifo (that is, the location of event1[7:0]). if the user tries to read back from any location in a fifo, data is always obtaine d from the top of th at fifo . this ensures that events can only be read back in the order in which they occurred , thus ensuring the integrity of the fifo system. as stated above, some of the onboard functions of adp5585 can be programmed to generate events on the fifo. a fifo update control block manages updates to the fifo. if an i 2 c transaction is accessing any of the fifo address locations, updates are paused until the i 2 c transaction has completed. a fifo overflow event occurs when more than 16 events ar e generated prior to an external processor reading a fifo and clear ing it. if an overflow condition occurs, the overflow status bit is set . a n interrupt is generated if overflow interrupt is enabled, signaling to the processor that more than 16 events have occurred. key scan control general the 10 input/output pins can be configured to decode a keypad matrix up to a maximum s ize of 25 switches (5 5 matrix). smaller matrices can also be configured, freeing up the unused row and column pins for other i/o fu nctions. the r0 through r4 i/o pins comprise the rows of the keypad matrix. the c0 through c4 i/o pins comprise the columns of the keyp ad matrix. pins used as rows are pulled up via the internal 300 k (or 100 k ) resistors. pins used as columns are driven low via the internal nmos current sink.
adp5585 data sheet rev. c | page 10 of 40 1 23 4 56 7 89 vdd r0 r1 r2 c2 c0 c1 3 3 keypad matrix 09841-008 key scan control figure 9. simplified key scan block figure 9 shows a simplified representation of the key scan block using three row and three column pins connected to a small 3 3, nine-switch keypad matrix. when the key scanner is idle, the row pins are pulled high and the column pins are driven low. the key scanner operates by checking the row pins to see if they are low. if switch 6 in the matrix is pressed, r1 connects to c2. the key scan circuit senses that one of the row pins has been pulled low, and a key scan cycle begins. key scanning involves driving all column pins high, then driving each column pin, one at a time, low and sensing whether a row pin is low or not. all row/column pairs are scanned; therefore, if multiple keys are pressed, they are detected. to prevent glitches or narrow press times being registered as a valid key press, the key scanner requires the key be pressed for two scan cycles. the key scanner has a wait time between each scan cycle; therefore, the key must be pressed and held for at least this wait time to register as being pressed. if the key is continuously pressed, the key scanner continues to scan, wait, scan, wait, and so forth. if switch 6 is released, the connection between r1 and c2 breaks, and r1 is pulled up high. the key scanner requires that the key be released for two scan cycles because the release of a key is not necessarily in sync with the key scanner, it may take up to two full wait/scan cycles for a key to register as released. when the key is registered as released, and no other keys are pressed, the key scanner returns to idle mode. for the remainder of this document, the press/release status of a key is represented as simply a logic signal in the figures. a logic high level represents the key status as pressed, and a logic low represents released. this eliminates the need to draw individual row/column signals when describing key events. key x key released key released key pressed 0 9841-009 figure 10. logic low: released, logic high: pressed figure 11 shows a detailed representation of the key scan block and its associated control and status signals. when all row and column pins are used, a matrix of 25 unique keys can be scanned. logic event 54321 10 9876 15 141312 11 20 19181716 25 24232221 30 29282726 i/o configuration key event gpi event i 2 c busy? r0 r3r1 r2 r4 r5 c0 c1 c2 c3 c4 pin_config_a[7:0] pin_config_b[7:0] fifo pin_config_c[7:0] event_int ovrflow_int ec[4:0] reset_trig_time[2:0] reset1_event_a[7:0] reset1_event_b[7:0] reset1_event_c[7:0] 31 33 36 32 35 34 reset2_event_a[7:0] reset2_event_b[7:0] reset 1_initiate reset 2_initiate 09841-010 fifo update key scan control column sink on/off row sense figure 11. detailed key scan block
data sheet adp5585 rev. c | page 11 of 40 use registers pin_config_a[7:0] and pin_config_b[7:0] to configure i/os for keypad decoding. the number label on each key switch represents the event identifier that is recorded if that switch was pressed. if all row/column pins are config- ured, it is possible to observe all 25 key identifiers on the fifo. a larger 6 5 matrix can be configured by using the adp5585acbz-01-r7 or the adp5585acpz-01-r7. if a smaller 2 2 matrix is configured, for example, by using the c2 and c3 column pins and the r1 and r2 row pins, only the four event identifiers (8, 9, 13, and 14) can possibly be observed on the fifo, as shown in figure 11. by default, adp5585 records key presses and releases on the fifo. figure 12 illustrates what happens when a single key is pressed and released. initially, the key scanner is idle. when key 3 is pressed, the scanner begins scanning through all configured row/column pairs. after the scan wait time, the scanner again scans through all configured row/column pairs and detects that key 3 has remained pressed, which sets the event_int interrupt. the event counter, ec[4:0], is incre- mented to 1, event1_identifier[6:0] of the fifo is updated with its event identifier set to 3, and its event1_state bit is set to 1, indicating a press. key 3 key 3 press key 3 release key scan event_int ec[4:0] fifo 1 2 1 0 0 0 3 3 0 0 09841-011 figure 12. press and release event the key scanner continues the scan/wait cycles while the key remains pressed. if the scanner detects that the key has been released for two consecutive scan cycles, the event counter, ec[4:0], is incremented to 2, and event2_identifier[6:0] of the fifo is updated with its event identifier set to 3. its event2_state bit is set to 0, indicating a release. the key scanner returns to idle mode because no other keys are pressed. the event_int interrupt can be triggered by both press and release key events. as shown in figure 14, if key 3 is pressed, event_int is asserted, ec[4:0] is updated, and the fifo is updated. during the time that the key remains pressed, it is possible for the fifo to be read, the event counter decremented to 0, and event_int cleared. when the key is finally released, event_int is asserted, the event counter is incremented, and the fifo is updated with the release event information. key 3 key 3 press key 32 release key scan event_int event_int cleared ec[4:0] fifo fifo read 0 0 0 0 0 0 0 0 fifo 1 0 0 0 3 0 0 0 fifo 101 0 0 0 0 3 0 0 0 09841-012 figure 13. asserting the event_int interrupt key pad extension as shown in figure 11, the keypad can be extended if each row is connected directly to ground by a switch. if the switch placed between r0 and ground is pressed, the entire row is grounded. when the key scanner completes scanning, it normally detects key 1 to key 5 as being pressed; however, this unique condition is decoded by the adp5585, and key event 31 is assigned to it. up to eight more key event assignments are possible, allowing the keypad size to extend up to 30. however, if one of the extended keys is pressed, none of the keys on that row is detectable. activation of a ground key causes all other keys sharing that row to be undetectable. ghosting ghosting is an occurrence where, given certain key press com- binations on a keypad matrix, a false positive reading of an additional key is detected. ghosting is created when three or more keys are pressed simultaneously on multiple rows or columns (see figure 14). key combinations that form a right angle on the keypad matrix can cause ghosting. the solution to ghosting is to select a keypad matrix layout that takes into account three key combinations that are most likely to be pressed together. multiple keys pressed across one row or across one column do not cause ghosting. staggering keys so that they do not share a column also avoids ghosting. the most common practice is to place keys that are likely to be pressed together in the same row or column. some examples of keys that are likely to be pressed together are as follows: ? the navigation keys in combination with select. ? the navigation keys in combination with the space bar. ? the reset combination keys, such as ctrl + alt + del. col0 row0 row1 row2 row3 press ghost press press col1 col2 09841-013 figure 14. col0: row3 is a ghost key due to a short among row0, col0, col2, and row3 during key press
adp5585 data sheet rev. c | page 12 of 40 gpi input each of the 10 input/output lines can be configured as a ge neral - purpose l ogic input line. figure 15 shows a detailed representation of the gpi scan and detect block and its associated control and status signals. pin_config_a[7:0] pin_config_b[7:0] gpi_int gpio 1 gpio 2 gpio 3 gpio 4 gpio 5 gpio 6 gpio 7 gpio 8 gpio 9 (r0) (r1) (r2) (r3) (r4) rst/(r5) (c0) (c1) (c2) gpio 10 gpio 1 1 (c3) (c4) gpi event ke y event ovrflow_int logic event gpi_int_level_a[7:0] gpi_int_level_b[7:0] gpi_interrupt_en_a[7:0] gpio_direction_a[7:0] gpi_s ta tus_a[5:0] gpi_s ta tus_b[4:0] gpi_int_s ta t_a[5:0] gpi_event_en_a[7:0] gpio_direction_b[7:0] gpi_interrupt_en_b[7:0] gpi_event_en_b[7:0] event_int gpi_int_s ta t_b[4:0] reset_trig_time[2:0] reset1_event_a[7:0] reset1_event_b[7:0] reset1_event_c[7:0] reset2_event_a[7:0] reset2_event_b[7:0] fifo1:fifo16 ec[4:0] 09841-014 fifo upd a te gpi scan contro l i 2 c busy figure 15 . gpi scan and detect block the current input state of each gpi can be r ead back using the gpi_status_x registers. each gpi can be programmed to generate an interrupt via the gpi_interrupt_en_x registers. the interrupt status is stored in the gpi_int_stat_x registers. gpi interrupts can be programmed to trigger on the positive or negative edge by configuring the gpi_int_level_x registers. if any of the gpi interrupts is triggered, the master gpi_int interrupt is also triggered. figure 16 show s a single gpi and how it affects its corresponding status an d interrupt status bits. gpi 3 gpi_s ta tus_a[3] gpi_interrupt_en_a[3] gpi_int_s ta t_a[3] gpi_int gpi_int_level_a[3] 09841-015 cleared b y read cleared b y write ?1 ? figure 16 . single gpi example gpis can be programmed to generate fifo events via the gpi_event_en_x registers. gpis in this mode do not generate gpi_int interrupts and instead generate event_int interrupt s. figure 17 shows several gpi lines and their effect s on the fifo and event count , ec[4:0] . gpi 2 gpi scan event_int ec[4:0] 1 6 gpi 2 active gpi 4 gpi 7 2 3 4 5 gpi 7 active gpi 4 active gpi 4 inactive gpi 7 inactive gpi 2 inactive fifo 1 1 1 0 0 0 38 38 43 43 40 40 09841-016 figure 17 . multiple gpi example the gpi scanner is idle until it detects a level transition. i t scans the gpi inputs and updates accordingly. it then returns to idle immediately, it does not scan/wait, like the key scanner. as such, the gpi s canner can detect narrow pulses once they get past the 50 s input debounce filter . gpo output each of the 10 input/output lines can be configured as a general - purpose output (gpo) line. figure 6 shows a detailed diagram of the i/o structure. see the detailed register descriptions section for gpo configuration and usage. logic blocks several of the adp5585 input/output lines can be used as inputs and outputs for implementing some common logic functions. the r1, r2, and r3 input/o utput pins can be used as inputs, and the r0 input/output pin can be used as an output for the logic b lock. the outputs from the logic blocks can be configured to generate interrupts. they can also be configured to generate events on the fifo . figure 19 shows a detailed diagram of the internal make - up of the logic block, illustrating the possible logic functions that can be implemented.
data sheet adp5585 rev. c | page 13 of 40 gpi event ke y event logic event (r1) l a lc lb la_inv d clr q set lb_inv lc_inv ff_set ff_clr r3_extend_cfg[1:0] logic_sel[2:0] l y_inv (r2) (r3) logic block l y (r0) logic_int logic_int_leve l logic_event_en ovrflow_int event_int reset_trig_time[2:0] reset1_event_a[7:0] reset1_event_b[7:0] reset1_event_c[7:0] reset2_event_a[7:0] reset2_event_b[7:0] fifo ec[4:0] 09841-017 logic event/int gener a t or i 2 c busy fifo upd a te figure 18 . logic block overview pwm block the adp55 85 features a pwm generator whose output can be configured to drive out on the r3 i/o pin . pwm on/off times are programmed via four 8 - bit registers (see figure 20 ). each bit of the on or off time represents 1 s. the highest frequency obtainable from the pwm is performed by setting the least significant bit of both the on and off time bit patterns, resulting in a 500 khz signal with a 50% duty cycle. the pwm block provides support for continuous pwm mode as well as a one - shot mode (see table 59 ). additionally, an external signal can be anded with the internal pwm signal. this option can be selected by writing a 1 to pwm_in_and ( pwm_cfg[2] ) . the input to the external and is the c3 i/o pin. c3 should be set to gpi. note that the debounce for c3 result s in a delay of the anding, and can be turned on or off using register 0x21. newly programmed values are not latched until the final byte, pwm_ont_high_byte ( register 0x32 , bits[ 7:0] ), is written. 09841-018 la_inv mux 000 001 sel[2:0] out 010 0 1 1 100 101 1 10 11 1 se l out 0 1 gnd and or xor ff in_l a in_lb in_lc l a l a l a in_l a se l out 0 1 and in_l a in_lb in_lc r3_extend_cfg[1:0] = 01 logic_sel[2:0] l y_inv se l out 0 1 l y l y l y lb_inv se l out 0 1 lb lb lb in_lb lc_inv se l out 0 1 lc lc lc in_lc ff_set ff_clr se l out 0 1 or in_l a in_lb in_lc and and or or se l out 0 1 xor in_l a in_lb in_lc in_l a in_lb in_lc xor xor d clr q set 0 1 se l out ff figure 19 . logic b l ock (c3) pwm_in off time[15:0] pwm_en pwm_in_and pwm_offt_low_byte[7:0] pwm_mode pwm_offt_high_byte[7:0] pwm_ont_low_byte[7:0] pwm_ont_high_byte[7:0] on time[15:0] sel out 0 1 09841-019 and pwm gener a t or (r3) pwm_out figure 20 . pwm block diagram
adp5585 data sheet rev. c | page 14 of 40 reset blocks adp5585 features two reset block s that can generate reset con - dition s if certain events are detected simultaneously . up to three reset trigger events can be programmed for reset 1 . up to two reset trigger eve nts can be programmed for reset 2. the event scan control blocks monitor whether these events are present for the duration of reset_trig_time [2:0] ( register 0x2 e , bi ts [4:2]) . if they are, reset - initiate signals are sent to the reset genera tor blocks. the generated reset signal pulse width is programmable. reset_pulse_width[1:0] reset_trig_time[2:0] reset1_event_a[7:0] reset1_event_b[7:0] reset1_event_c[7:0] k ey s ca n c on t r o l rst_passthru_en rst (r4) reset1 g p i s ca n c on t r o l log i c b l o c k c on t r o l reset2_event_a[7:0] reset2_event_b[7:0] (c4) reset2 reset1_ initiate reset2_ initiate reset gen 2 reset gen 1 09841-020 figure 21 . reset blocks the r eset 1 s ignal uses the r4 i/o pin as its output . a pass th rough mode allows the main rst pin to be output on the r 4 pin also . the r eset 2 signal uses the c4 i/o pin as its output . the reset generation signal s are useful in situations where the system processor has locked up and the system i s unresponsive to input events. the user can press one of the reset event combi - nation s and initiate a system wide reset. this alleviates the need for removing the battery from the system and doing a hard reset. it is not recommended to use the immediate trigger time (see table 54) because this setting may cause false triggering. interrupts the int pin can be asserted low if any of the internal interrupt sources is active. the user can select which internal interrupts interact with the external interrupt pin in register 0x3c (refer to table 68 ). register 0x3b allows the user to choose whether the external interrupt pin remains asserted , or deasserts fo r 50 s, then reasserts, in the case that there are multiple internal interrupts asserted and one is cleared (refer to table 67). event_int event_ien int drive int int_cfg gpi_int gpi_ien logic_int logic_ien ovrflow_int ovrflow_ien 09841-021 figure 22 . asserting int low
data sheet adp5585 rev. c | page 15 of 40 register interface register access to the adp5585 is acquired via its i 2 c-compatible serial interface. the interface can support clock frequencies of up to 1 mhz. if the user is accessing the fifo or key event counter (kec), fifo/kec updates are paused. if the clock frequency is very low, events may not be recorded in a timely manner. fifo or kec updates can happen up to 23 s after an interrupt is asserted because of the number of i 2 c cycles required to perform an i 2 c read or write. this delay should not present an issue to the user. figure 23 shows a typical write sequence for programming an internal register. the cycle begins with a start condition, followed by the hard coded 7-bit device address, which for the adp5585 is 0x34, followed by the r/ w bit set to 0 for a write cycle. the adp5585 acknowledges the address byte by pulling the data line low. the address of the register to which data is to be written is sent next. the adp5585 acknowledges the register pointer byte by pulling the data line low. the data byte to be written is sent next. the adp5585 acknowledges the data byte by pulling the data line low. a stop condition completes the sequence. figure 24 shows a typical multibyte write sequence for program- ming internal registers. the cycle begins with a start condition followed by the 7-bit device address (0x34 for all models except the adp5585acpz-03-r7, 0x30 for the adp5585acpz-03-r7 only), followed by the r/ w bit set to 0 for a write cycle. the adp5585 acknowledges the address byte by pulling the data line low. the address of the register to which data is to be written is sent next. the adp5585 acknowledges the register pointer byte by pulling the data line low. the data byte to be written is sent next. the adp5585 acknowledges the data byte by pulling the data line low. the pointer address is then incremented to write the next data byte, until it finishes writing the n data byte. the adp5585 pulls the data line low after every byte, and a stop condition completes the sequence. figure 25 shows a typical byte read sequence for reading inter- nal registers. the cycle begins with a start condition followed by the 7-bit device address (0x34 for all models except the adp5585acpz-03-r7, 0x30 for the adp5585acpz-03-r7 only), followed by the r/ w bit set to 0 for a write cycle. the adp5585 acknowledges the address byte by pulling the data line low. the address of the register from which data is to be read is sent next. the adp5585 acknowledges the register pointer byte by pulling the data line low. a start condition is repeated, followed by the 7-bit device addr ess (0x34 for all models except the adp5585acpz-03-r7, 0x30 for the adp5585acpz-03-r7 only), followed by the r/ w bit set to 1 for a read cycle. the adp5585 acknowledges the address byte by pulling the data line low. the 8-bit data is then read. the host pulls the data line high (no acknowledge), and a stop condition completes the sequence. start 0 = write 7-bit device address adp5585 ack 8-bit register pointer 8-bit write data 0000 adp5585 ack adp5585 ack stop 09841-022 figure 23. i 2 c single byte write sequence start 0 = write 7-bit device address adp5585 ack 8-bit register pointer write byte 1 write byte 2 write byte n 00 0 0 0 0 0 adp5585 ack adp5585 ack adp5585 ack adp5585 ack adp5585 ack stop 09841-023 figure 24. i 2 c multibyte write sequence start 0 = write 7-bit device address 7-bit device address adp5585 ack 8-bit register pointer 8-bit read data 00 0 1 0 1 repe a t st a rt 1 = read adp5585 ack adp5585 ack no ack stop 09841-024 figure 25. i 2 c single byte read sequence
adp5585 data sheet rev. c | page 16 of 40 figure 26 shows a typical multibyte read sequence for reading internal registers. the cycle begins with a start condition, followed by the 7-bit device address (0x34 for all models except the adp5585acpz-03-r7, 0x30 for the adp5585acpz-03-r7 only), followed by the r/ w bit set to 0 for a write cycle. the adp5585 acknowledges the address byte by pulling the data line low. the address of the register from which data is to be read is sent next. the adp5585 acknowledges the register pointer byte by pulling the data line low. a start condition is repeated, followed by the 7-bit device address (0x34 for all models except the adp5585acpz-03-r7, 0x30 for the adp5585acpz-03-r7 only), followed by the r/ w bit set to 1 for a read cycle. the adp5585 acknowledges the address byte by pulling the data line low. the 8-bit data is then read. the address pointer is then incremented to read the next data byte, and the host continues to pull the data line low for each byte (master acknowledge) until the n data byte is read. the host pulls the data line high (no acknowledge) after the last byte is read, and a stop condition completes the sequence. start 0 = write 7-bit device address 7-bit device address adp5585 ack 8-bit register pointer read byte 1 read byte 2 read byte n 00 0 1 0 0 0 0 1 repe a t s t a rt 1 = rea d adp5585 ack adp5585 ack master ack master ack master ack no ack stop 09841-025 figure 26. i 2 c multibyte read sequence
data sheet adp5585 rev. c | page 17 of 40 register map table 6 . reg add reg name r/w 1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x00 id r man_id rev_id 0x01 int_status r/w reserved logic_int reserved ovrflow_ int gpi_int event_int 0x02 status r reserved logic_stat reserved ec[4:0] 0x03 fifo_1 r event1_state event1_identifier[6:0] 0x04 fifo_2 r event2_state event2_identifier[6:0] 0x05 fifo_3 r event3_state event3_identifier[6:0] 0x06 fifo_ 4 r event4_state event4_identifier[6:0] 0x07 fifo_5 r event5_state event5_identifier[6:0] 0x08 fifo_6 r event6_state event6_identifier[6:0] 0x09 fifo_7 r event7_state event7_identifier[6:0] 0x0a fifo_8 r event8_state event8_identifier[6:0] 0x0b fifo_9 r event9_state event9_identifier[6:0] 0x0c fifo_10 r event10_state event10_identifier[6:0] 0x0d fifo_11 r event11_state event11_identifier[6:0] 0x0e fifo_12 r event12_state event12_identifier[6:0] 0x0f fifo_13 r event13_state event13_identifier[6:0] 0x10 fifo_14 r event14_state event14_identifier[6:0] 0x11 fifo_15 r event15_state event15_identifier[6:0] 0x12 fifo_16 r event16_state event16_identifier[6:0] 0x13 gpi_int_ stat_a r reserved gpi_6_int gpi_5_int gpi_4_int gpi_3_int gpi_2_int gpi_1_int 0 x14 gpi_int_ stat_b r reserved gpi_11_int gpi_10_int gpi_9_int gpi_8_int gpi_7_int 0x15 gpi_status_a r reserved gpi_6_stat gpi_5_stat gpi_4_stat gpi_3_stat gpi_2_stat gpi_1_stat 0x16 gpi_status_b r reserved gpi_11_stat gpi_10_stat gpi_9_stat gpi_8_stat g pi_7_stat 0x17 r_pull_ config_a r/w r3_pull_cfg r2_pull_cfg r1_pull_cfg r0_pull_cfg 0x18 r_pull_ config_b r/w reserved r5_pull_cfg r4_pull_cfg 0x19 r_pull_ config_c r/w c3_pull_cfg c2_pull_cfg c1_pull_cfg c0_pull_cfg 0x1a r_pull_ config_d r/w reserved c4_pull_cfg 0x1b gpi_int_ level_a r/w reserved gpi_6_ int_level gpi_5_ int_level gpi_4_ int_level gpi_3_ int_level gpi_2_ int_level gpi_1_ int_level 0x1c gpi_int_ level_b r/w reserved gpi_11_ int_level gpi_10_ int_level gpi_9_ int_level gpi_8_ int_level gpi_7_ int_level 0x1d gpi_event_en_a r/w reserved gpi_6_ event_en gpi_5_ event_en gpi_4_ event_en gpi_3_ event_en gpi_2_ event_en gpi_1_ event_en 0x1e gpi_event_en_b r/w reserved gpi_11_ event_en gpi_10_ event_en gpi_9_ event_en gpi_8_ event_e n gpi_7_ event_en 0x1f gpi_interrupt_ en_a r/w reserved gpi_6_ int_en gpi_5_ int_en gpi_4_ int_en gpi_3_ int_en gpi_2_ int_en gpi_1_ int_en 0x20 gpi_interrupt_ en_b r/w reserved gpi_11_ int_en gpi_10_ int_en gpi_9_ int_en gpi_8_ int_en gpi_7_ int_en 0x2 1 debounce_ dis_a r/w reserved gpi_6_ deb_dis gpi_5_ deb_dis gpi_4_ deb_dis gpi_3_ deb_dis gpi_2_ deb_dis gpi_1_ deb_dis 0x22 debounce_ dis_b r/w reserved gpi_11_ deb_dis gpi_10_ deb_dis gpi_9_ deb_dis gpi_8_ deb_dis gpi_7_ deb_dis 0x23 gpo_data_ out_a r /w reserved gpo_6_ data gpo_5_ data gpo_4_ data gpo_3_ data gpo_2_ data gpo_1_ data 0x24 gpo_data_ out_ b r/w reserved gpo_11_ data gpo_10_ data gpo_9_ data gpo_8_ data gpo_7_ data 0x25 gpo_out_ mode_a r/w reserved gpo_6_ out_mode gpo_5_ out_mode gpo_4_ o ut_mode gpo_3_ out_mode gpo_2_ out_mode gpo_1_ out_mode
adp5585 data sheet rev. c | page 18 of 40 reg add reg name r/w 1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x26 gpo_out_ mode_b r/w reserved gpo_11_ out_mode gpo_10_ out_mode gpo_9_ out_mode gpo_8_ out_mode gpo_7_ out_mode 0x27 gpio_ direction_a r/w reserved gpo_6_ dir gpo_5_ dir gpo_4_ dir gpo_3_ dir gp o_2_ dir gpo_1_ dir 0x28 gpio_ direction_b r/w reserved gpo_11_ dir gpo_10_ dir gpo_9_ dir gpo_8_ dir gpo_7_ dir 0x29 reset1_event_a r/w reset1_ event_ a_level reset1_event_a [6:0] 0x2a reset1_event_b r/w reset1_ event_ b_level reset1_event_b [6:0] 0x2 b reset1_event_c r/w reset1_ event_ c_level reset1_event_c [6:0] 0x2c reset2_event_a r/w reset2_ event_ a_level reset2_event_a [6:0] 0x2d reset2_event_b r/w reset2_ event_ b_level reset2_event_b [6:0] 0x2e reset2_cfg r/w reset2_pol reset1_pol rst _pass thru_en reset_trig_time [2:0] reset_pulse_width[1:0] 0x2f pwm_offt_low r/w pwm_offt_low_byte[7:0] 0x30 pwm_offt_high r/w pwm_offt_high_byte[7:0] 0x31 pwm_ont_low r/w pwm_ont_low_byte[7:0] 0x32 pwm_ont_high r/w pwm_ont_high_byte[7:0] 0x 33 pwm_cfg r/w reserved pwm_in_ and pwm_mode pwm_en 0x34 logic_cfg r/w reserved ly_inv lc_inv lb_inv la_inv logic_sel[2:0] 0x35 logic_ff_cfg r/w reserved ff_set ff_clr 0x36 logic_int_ event_en r/w reserved ly_dbnc_ dis logic_ event_en logic_int_ level 0x37 poll_time_cfg r/w reserved key_poll_time[1:0] 0x38 pin_config_a r/w reserved r5_config r4_config r3_config r2_config r1_config r0_config 0x39 pin_config_b r/w reserved c4_config c3_config c2_config c1_config c0_config 0x3a pin_config_ c r/w pull_sel ect c4_extend_cfg r4_extend _cfg reserved r3_extend_cfg[1:0] reserved r0_extend _cfg 0x3b general_cfg r/w osc_en core_freq[1:0] reserved int _cfg rst _cfg 0x3c int_en r/w reserved logic_ien reserved ovrflow_ ien gpi_ien event_ien 1 r means read, w means write, and r/w means read/write.
data sheet adp5585 rev. c | page 19 of 40 detailed register de scriptions note that n/a throughout this section means not applicable. note: all register default to 0000 0000 unless otherwise specified. id register 0x00 table 7 . id bit descriptions bit ( s ) bit n ame access description 7 to 4 man_id read only manufacturer id, default = 0010 3 to 0 rev_id read only rev id int_status register 0x01 table 8 . int_status bit descriptions bit ( s ) bit name access description 1 7 to 5 n/a reserved . 4 logic_int read/write 0 = no interrupt . 1 = interrupt due to a general logic condition . 3 n/a reserved . 2 overflow_int read/write 0 = no interrupt . 1 = interrupt due to an overflow condition . 1 gpi_int read/write this bit is not set by a gp i that has been configured to update the fifo and event count. this bit cannot be cleared until all gpi_x_int bits are cleared . 0 = no interrupt . 1 = interrupt due to a general gpi condition . 0 event_int read/write 0 = no interrupt . 1 = in terrupt due to key event (press/release), gpi event (gpi pr ogrammed for fifo updates), or logic event (programmed for fifo updates) . 1 interrupt bits are cleared by writing a 1 to the flag; writing a 0 or reading the flag has no effect. status register 0x02 table 9 . status bit descriptions bit ( s ) bit name access description 7 n/a reserved . 6 logic_stat read only 0 = o utput from logic block (ly) is low . 1 = o utput from logic block (ly) is high. 5 n/a reserved . 4 to 0 ec[4:0] read only event count value. indicates how many events are currently stored on the fifo. fifo_1 regi ster 0x03 table 10. fifo_1 bit descriptions bit ( s ) bit name access description 7 event1_state read only this bit represents the state of the event that is recorded in the event1_identifier[6:0] bit . for key events from event 1 to event 36 , use the following settings: 1 = key is pressed. 0 = key is released. for gpi and logic events from event 37 to event 4 8 , use the following settings: 1 = gpi/logic is active. 0 = gpi/logic is inactive. active and inactiv e states for event 37 to event 48 are programmable. 6 to 0 event1_identifier[6:0] read only contains the event identifier for the pin. refer to table 11.
adp5585 data sheet rev. c | page 20 of 40 table 11 . event decoding event no. meaning event no. meaning event no. meaning event no. meaning 0 no event 32 key 32 (r1, gnd) 64 unused 96 unused 1 key 1 (r0, c0) 33 key 33 (r2, gnd) 65 unused 97 unused 2 key 2 (r0, c1) 34 key 34 (r3, gnd) 66 unused 98 unused 3 key 3 (r0, c2) 35 k ey 35 (r4, gnd) 67 unused 99 unused 4 key 4 (r0, c3) 36 key 36 (r5, gnd) 68 unused 100 unused 5 key 5 (r0, c4) 37 gpi 1 (r0) 69 unused 101 unused 6 key 6 (r1, c0) 38 gpi 2 (r1) 70 unused 102 unused 7 key 7 (r1, c1) 39 gpi 3 (r2) 71 unused 103 unused 8 key 8 (r1, c2) 40 gpi 4 (r3) 72 unused 104 unused 9 key 9 (r1, c3) 41 gpi 5 (r4) 73 unused 105 unused 10 key 10 (r1, c4) 42 gpi 6 (r5) 74 unused 106 unused 11 key 11 (r2, c0) 43 gpi 7 (c0) 75 unused 107 unused 12 key 12 (r2, c1) 44 gpi 8 (c1) 76 unuse d 108 unused 13 key 13 (r2, c2) 45 gpi 9 (c2) 77 unused 109 unused 14 key 14 (r2, c3) 46 gpi 10 (c3) 78 unused 110 unused 15 key 15 (r2, c4) 47 gpi 11 (c4) 79 unused 111 unused 16 key 16 (r3, c0) 48 logic 80 unused 112 unused 17 key 17 (r3, c1) 49 unu sed 81 unused 113 unused 18 key 18 (r3, c2) 50 unused 82 unused 114 unused 19 key 19 (r3, c3) 51 unused 83 unused 115 unused 20 key 20 (r3, c4) 52 unused 84 unused 116 unused 21 key 21 (r4, c0) 53 unused 85 unused 117 unused 22 key 22 (r4, c1) 54 unus ed 86 unused 118 unused 23 key 23 (r4, c2) 55 unused 87 unused 119 unused 24 key 24 (r4, c3) 56 unused 88 unused 120 unused 25 key 25 (r4, c4) 57 unused 89 unused 121 unused 26 key 26 (r5, c0) 58 unused 90 unused 122 unused 27 key 27 (r5, c1) 59 unuse d 91 unused 123 unused 28 key 28 (r5, c2) 60 unused 92 unused 124 unused 29 key 29 (r5, c3) 61 unused 93 unused 125 unused 30 key 30 (r5, c4) 62 unused 94 unused 126 unused 31 key 31 (r0, gnd) 63 unused 95 unused 127 unused fifo_2 register 0x04 table 12 . fifo_2 bit descriptions bit(s) bit name access description 7 event2_state read only refer to table 10. 6 to 0 event2_identifier[6:0] read only refer to table 10. fifo_3 register 0x05 table 13 . fifo_3 bit descriptions bit(s) bit name access description 7 event3_state read only refer to table 10. 6 to 0 event3_identifier[6:0] rea d only refer to table 10. fifo_4 register 0x06 table 14 . fifo_4 bit descriptions bit(s) bit name access description 7 event4_state read only refer to table 10. 6 to 0 event4_identifier[6:0] read only refer to table 10.
data sheet adp5585 rev. c | page 21 of 40 fifo_5 register 0x07 table 15 . fifo_5 bit descriptions bit(s) bit name access description 7 event5_state read only refer to table 10. 6 to 0 event5_identifier[6:0] read only refer to table 10. fifo_6 register 0x08 table 16 . fifo_6 bit descriptions bit(s) bit n ame access description 7 event6_state read only refer to table 10 . 6 to 0 event6_identifier[6:0] read only refer to table 10. fifo_7 register 0x09 table 17 . fifo_7 bit descriptions bit(s) bit name access description 7 event7_state read only refer to table 10. 6 to 0 event7_identifier[6:0] read only refer to table 1 0 . fifo_8 register 0x0a table 18 . fifo_8 bit descriptions bit(s) bit name access description 7 event8_state read only refer to table 10. 6 to 0 event8_identifier[6:0] read only refer to table 10 . fifo_9 register 0x0b table 19 . fifo_9 bit descriptions bit(s) bit name access description 7 event9_state read only refer to table 10. 6 to 0 event9_identifier[6:0] read only refer to table 10. fifo_10 register 0x0c table 20 . fifo_10 bit descriptions bit(s) bit name access description 7 event10_state read only refer to table 10. 6 to 0 event10_identifier[6:0] read only refer to table 10. fifo_11 register 0x0d table 21 . fifo_11 bit descriptions bit(s) bit name access description 7 event11_state read only refer to table 10 . 6 to 0 event11_identifier[6:0] read only refer to table 10. fifo_12 register 0x0e table 22 . fifo_12 bit descriptions bit(s) bit name access description 7 event12_state read only refer to table 10. 6 to 0 event12_identifier[6:0] read only refer to table 10.
adp5585 data sheet rev. c | page 22 of 40 fifo_ 13 register 0x0 f table 23 . fifo_13 bit descriptions bit(s) bit name access description 7 event13_state read only refer to table 10. 6 to 0 event13_identifier[6:0] read only refer to table 10. fifo_ 14 register 0x 10 table 24 . fifo_14 bit descriptions bit(s) bit name access description 7 event14_state read only refer to table 10 . 6 to 0 event14_identifier[6:0] read only refer to table 10. fifo_ 1 5 register 0x 11 table 25 . fifo_15 bit descriptions bit(s) bit name access description 7 event15_state read only refer to table 10. 6 to 0 event15_identifier[6:0] read only refer to table 10. fifo_ 16 register 0x 12 table 26 . fifo_16 bit descriptions bit(s) bit name ac cess description 7 event16_state read only refer to table 10. 6 to 0 event16_identifier[6:0] read only refer to table 10 . gpi_int_stat_a register 0x13 table 27 . gpi_int_stat_a bit descriptions bit(s) bit name access description 7 to 6 n/a reserved . 5 gpi_6_int read only 0 = no interrupt 1 = interrupt due to gpi_6 (r5 pin). cleared on read. 4 gpi_5_int read only 0 = no interrupt 1 = inte rrupt due to gpi_5 (r4 pin). cleared on read. 3 gpi_4_int read only 0 = no interrupt 1 = interrupt due to gpi_4 (r3 pin). cleared on read. 2 gpi_3_int read only 0 = no interrupt 1 = interrupt due to gpi_3 (r2 pin). cleared on read. 1 gpi_2_int r ead only 0 = no interrupt 1 = interrupt due to gpi_2 (r1 pin). cleared on read. 0 gpi_1_int read only 0 = no interrupt 1 = interrupt due to gpi_1 (r0 pin). cleared on read. gpi_int_stat_b register 0x14 table 28 . gpi_int_s tat_b bit descriptions bit(s) bit name access description 7 to 5 n/a reserved . 4 gpi_11_int read only 0 = no interrupt . 1 = interrupt due to gpi_11 (c4 pin). cleared on read. 3 gpi_10_int read only 0 = no interrupt . 1 = interrupt due to gpi_10 (c3 pin). cleared on read.
data sheet adp5585 rev. c | page 23 of 40 bit(s) bit name access description 2 gpi_ 9 _int read only 0 = no interrupt . 1 = interrupt due to gpi_9 (c2 pin). cleared on read. 1 gpi_8_int read only 0 = no interrupt . 1 = interrupt due to gpi_8 (c1 pin). cleared on read. 0 gpi_7_int read only 0 = no i nterrupt . 1 = interrupt due to gpi_7 (c0 pin). cleared on read. gpi_status_a register 0x15 table 29. gpi_status_a bit descriptions bit(s) bit name access description 7 to 6 n/a reserved . 5 gpi_6_ stat read only 0 = gpi_6 (r5 pin) is low. 1 = gpi_6 (r5 pin) is high. 4 gpi_5_ stat read only 0 = gpi_5 (r4 pin) is low. 1 = gpi_5 (r4 pin) is high. 3 gpi_4_ stat read only 0 = gpi_4 (r3 pin) is low. 1 = gpi_4 (r3 pin) is high. 2 gpi_3_ stat read only 0 = gpi_3 (r2 pin) is low. 1 = gpi_3 (r2 pin) is high. 1 gpi_2_ stat read only 0 = gpi_2 (r1 pin) is low. 1 = gpi_2 (r1 pin) is high. 0 gpi_1_stat read only 0 = gpi_1 (r0 pin) is low. 1 = gpi_1 (r0 pin) is high. gpi_status_b register 0x16 table 30 . register 0x16, gpi_status_b bit descriptions bit(s) bit name access description 7 to 5 n/a reserved . 4 gpi_11_ stat read only 0 = gpi_11 (c4 pin) is low. 1 = gpi_11 (c4 pin) is high. 3 gpi_10_ stat read only 0 = gpi_10 (c3 pin) is low. 1 = gpi_10 (c3 pin) is high. 2 gpi_9_ stat read only 0 = gpi_9 (c2 pin) is low. 1 = gpi_9 (c2 pin) is high. 1 gpi_8_ stat read only 0 = gpi_8 (c1 pin) is low. 1 = gpi_8 (c1 pin) is high. 0 gpi_7_stat read only 0 = gpi_7 (c0 pin) is low. 1 = gp i_7 (c0 pin) is high.
adp5585 data sheet rev. c | page 24 of 40 rpull_config_a register 0x17 table 31 . rpull_config_a bit descriptions bit(s) bit name access description 7 to 6 r3_pull_cfg read/write 00 = enable 300 k? pull -up resistor . 01 = enable 300 k? pull - down re sistor. 10 = enable 100 k? pull - up resistor. 11 = disable all pull - up/pull- down resistors. 5 to 4 r2_pull_cfg read/write 00 = enable 300 k? pull - up resistor. 01 = enable 300 k? pull - down resistor. 10 = enable 100 k? pull - up resistor. 1 1 = disable all pull - up/pull- down resistors. 3 to 2 r1_pull_cfg read/write 00 = enable 300 k? pull -up resistor. 01 = enable 300 k? pull - down resistor. 10 = enable 100 k? pull - up resistor. 11 = disable all pull - up/pull- down resistors. 1 to 0 r 0_pull_cfg read/write 00 = enable 300 k? pull -up resistor. 01 = enable 300 k? pull - down resistor. 10 = enable 100 k? pull - up resistor. 11 = disable all pull - up/pull- down resistors. adp5585ac_z -00- r7, adp5585ac_z -01- r7, adp5585acpz -03 - r7 defaul t = 0000 0000 adp5585acbz -02- r7 default = 1100 0011 adp5585acbz - 04 - r7 default = 0101 0101 rpull_config_b register 0x18 table 32. rpull_config _b bit descriptions bit(s) bit name access description 7 to 4 n/a reserved . 3 to 2 r5 _pull_cfg read/write (reserved except for adp5585acbz -01- r7 options) 00 = enable 300 k? pull - up resistor. 01 = enable 300 k? pull - down resistor. 10 = enable 100 k? pull - up resistor. 11 = disable all pull - up/pull- down resistors. 1 to 0 r4_pull_cfg read/write 00 = enable 300 k? pull -up resistor. 01 = enable 3 00 k? pull - down resistor. 10 = enable 100 k? pull - up resistor. 11 = disable all pull - up/pull- down resistors. adp5585ac_z -00- r7, adp5585ac_z -01- r7, adp5585acpz -03 - r7 default = 0000 0000 adp5585acbz -02- r7 default = 0000 0011 adp5585acbz -04- r7 defa ult = 0000 0101
data sheet adp5585 rev. c | page 25 of 40 rpull_config_c register 0x19 table 33. rpull_config _c bit descriptions bit(s) bit name access description 7 to 6 c3_pull_cfg read/write 00 = enable 300 k? pull -up resistor . 01 = enable 300 k? pull - down resistor . 10 = enable 100 k? pull - up resistor. 11 = disable all pull - up/pull- down resistors. 5 to 4 c2_pull_cfg read/write 00 = enable 300 k? pull - up resistor. 01 = enable 300 k? pull - down resistor. 10 = enable 100 k? pull - up resistor. 11 = di sable all pull - up/pull- down resistors. 3 to 2 c1_pull_cfg read/write 00 = enable 300 k? pull -up resistor. 01 = enable 300 k? pull - down resistor. 10 = enable 100 k? pull - up resistor. 11 = disable all pull - up/pull- down resistors. 1 to 0 c0_pull _cfg read/write 00 = enable 300 k? pull -up resistor. 01 = enable 300 k? pull - down resistor. 10 = enable 100 k? pull - up resistor. 11 = disable all pull - up/pull- down resistors. adp5585ac_z -00- r7, adp5585ac_z -01- r7, adp5585acbz -02 - r7 , adp5585acp z -03- r7 default = 0000 0000 adp5585acbz -04- r7 default = 0101 0101 rpull_config_d register 0x1a table 34. rpull_config _d bit descriptions bit(s) bit name access description 7 to 2 n/a reserved . 1 to 0 c4_pull_cfg read/write 00 = enable 300 k? pull -up resistor. 01 = enable 300 k? pull - down resistor. 10 = enable 100 k? pull - up resistor. 11 = disable all pull - up/pull- down resistors. adp5585ac_z -00- r7, adp5585ac_z -01- r7, adp5585acpz -03 - r7 default = 0000 0000 adp5585acbz -02- r7 default = 0000 0011 adp5585acbz -04- r7 default = 0000 0001 gpi_int_level_a register 0x1b table 35 . gpi_int_level_a bit descriptions bit(s) bit name access description 7 to 6 n/a reserved . 5 gpi_6_int_level read/write (re served except for adp5585ac_z -01- r7 options) 0 = gpi_6 interrupt is active low (gpi_6_int sets whenever r5 is low). 1 = gpi_6 interrupt is active high (gpi_6_int sets whenever r5 is high). 4 gpi_5_int_level read/write 0 = gpi_5 interrupt is active low (gpi_5_int sets whenever r4 is low). 1 = gpi_5 interrupt is active high (gpi_5_int sets whenever r4 is high). 3 gpi_4_int_level read/write 0 = gpi_4 interrupt is active low (gpi_4_int sets whenever r3 is low). 1 = gpi_4 interrupt is active hi gh (gpi_4_int sets whenever r3 is high). 2 gpi_3_int_level read/write 0 = gpi_3 interrupt is active low (gpi_3_int sets whenever r2 is low). 1 = gpi_3 interrupt is active high (gpi_3_int sets whenever r2 is high). 1 gpi_2_int_level read/write 0 = gpi _2 interrupt is active low (gpi_2_int sets whenever r1 is low). 1 = gpi_2 interrupt is active high (gpi_2_int sets whenever r1 is high). 0 gpi_1_int_level read/write 0 = gpi_1 interrupt is active low (gpi_1_int sets whenever r0 is low). 1 = gpi_1 interrupt is active high (gpi_1_int sets whenever r0 is high).
adp5585 data sheet rev. c | page 26 of 40 gpi_int_level_b register 0x1c table 36 . register 0x1c, gpi_int_level_b bit descriptions bit(s) bit name access description 7 to 5 n/a reserved . 4 gpi_11_int_level re ad/write 0 = gpi_11 interrupt is active low (gpi_11_int sets whenever r10 is low). 1 = gpi_11 interrupt is active high (gpi_11_int sets whenever r10 is high). 3 gpi_10_int_level read/write 0 = gpi_10 interrupt is active low (gpi_10_int sets whenever r 9 is low). 1 = gpi_10 interrupt is active high (gpi_10_int sets whenever r9 is high). 2 gpi_9_int_level read/write 0 = gpi_9 interrupt is active low (gpi_9_int sets whenever r8 is low). 1 = gpi_9 interrupt is active high (gpi_9_int sets whenever r 8 is high). 1 gpi_8_int_level read/write 0 = gpi_8 interrupt is active low (gpi_8_int sets whenever r7 is low). 1 = gpi_8 interrupt is active high (gpi_8_int sets whenever r7 is high). 0 gpi_7_int_level read/write 0 = gpi_7 interrupt is active low (g pi_7_int sets whenever r6 is low). 1 = gpi_7 interrupt is active high (gpi_7_int sets whenever r6 is high). gpi_event_en_a register 0x1d table 37 . gpi_event_en_a bit descriptions bit(s) bit name access description 7 to 6 n/a reserved . 5 gpi_6_event_en read/write (reserved except for adp5585ac_z -01- r7 options) 0 = disable gpi events from gpi 6. 1 = allow gpi 6 activity to generate events on the fifo 1 . 4 gpi_5_event_en read/write 0 = disable gpi events from gpi 5. 1 = allow gpi 5 activity to generate events on the fifo 1 . 3 gpi_4_event_en read/write 0 = disable gpi events from gpi 4. 1 = allow gpi 4 activity to generate events on the fifo 1 . 2 gpi_3_event_en read/write 0 = disable gpi events from gpi 3. 1 = allow gpi 3 activity to generate events on the fifo 1 . 1 gpi_2_event_en read/write 0 = disable gpi events from gpi 2. 1 = allow gpi 2 activity to generate events on the fifo 1 . 0 gpi_1_event_en read/write 0 = disable gpi events from gpi 1. 1 = allow gpi 1 activity to generate events on the fifo 1 . 1 gpis in this mode are considered fifo events and c an be used for unlock purposes. gpi activity in this mode causes event _int interrupts. gpis in this mode do not generate gpi_int i nterrupts. gpi_event_en_b register 0x1e table 38 . gpi_event_en_b bit descriptions bit(s) bit name access description 7 to 5 n/a reserved . 4 gpi_11_event_en read/write 0 = disable gpi events from gpi 11. 1 = all ow gpi 11 activity to generate events on the fifo 1 . 3 gpi_10_event_en read/write 0 = disable gpi events from gpi 10. 1 = allow gpi 10 activity to generate events on the fifo 1 . 2 gpi_9_event_en read/write 0 = disable gpi events from gpi 9. 1 = all ow gpi 9 activity to generate events on the fifo 1 . 1 gpi_8_event_en read/write 0 = disable gpi events from gpi 8. 1 = allow gpi 8activity to generate events on the fifo 1 . 0 gpi_7_event_en read/write 0 = disable gpi events from gpi 7. 1 = allow gp i 7 activity to generate events on the fifo 1 . 1 gpis in this mode are considered fifo events and can be used for unlock purposes. gpi activity in this mode cause event_int i nterrupts. gpis in this mode do not generate gpi_int interrupts.
data sheet adp5585 rev. c | page 27 of 40 gpi_event_interr upt_en_a register 0x1f table 39 . gpi_interrupt_en_a bit descriptions bit(s) bit name access description 7 to 6 n/a reserved . 5 gpi_6_int_en read/write (reserved except for adp5585ac_z -01- r7 options) 0 = gpi_6_int is disabled. 1 = gpi_6_int enabled. asserts the gpi_int bit (register 0x01, bit 1) if gpi_6_int is set and the gpi 6 interrupt condition is met. 4 gpi_5_int_en read/write 0 = gpi_5_int is disabled. 1 = gpi_5_int enabled. asserts the gpi_int bit (register 0x01 , bit 1) if gpi_5_int is set and the gpi 5 interrupt condition is met. 3 gpi_4_int_en read/write 0 = gpi_4_int is disabled. 1 = gpi_4_int enabled. asserts the gpi_int bit (register 0x01, bit 1) if gpi_4_int is set and the gpi 4 interrupt condition is met. 2 gpi_3_int_en read/write 0 = gpi_3_int is disabled. 1 = gpi_3_int enabled. asserts the gpi_int bit (register 0x01, bit 1) if gpi_3_int is set and the gpi 3 interrupt condition is met. 1 gpi_2_int_en read/write 0 = gpi_2_int is disabled. 1 = gpi_2_int enabled. asserts the gpi_int bit (register 0x01, bit 1) if gpi_2_int is set and the gpi 2 interrupt condition is met. 0 gpi_1_int_en read/write 0 = gpi_1_int is disabled. 1 = gpi_1_int enabled. asserts the gpi_int bit (register 0x01, bit 1) if gpi_1_int is set and the gpi 1 interrupt condition is met. gpi_event_interrupt_en_b register 0x20 table 40 . gpi_interrupt_en_b bit descriptions bit(s) bit name access description 7 to 5 n/a reserved . 4 gpi_11_int_en read/wri te 0 = gpi_11_int is disabled. 1 = gpi_11_int enabled. asserts the gpi_int bit (register 0x01, bit 1) if gpi_11_int is set and the gpi 11 interrupt condition is met. 3 gpi_10_int_en read/write 0 = gpi_10_int is disabled. 1 = gpi_10_int enabled. as serts the gpi_int bit (register 0x01, bit 1) if gpi_10_int is set and the gpi 10 interrupt condition is met. 2 gpi_9_int_en read/write 0 = gpi_9_int is disabled. 1 = gpi_9_int enabled. asserts the gpi_int bit (register 0x01, bit 1) if gpi_9_int is set and the gpi 9 interrupt condition is met. 1 gpi_8_int_en read/write 0 = gpi_8_int is disabled. 1 = gpi_8_int enabled. asserts the gpi_int bit (register 0x01, bit 1) if gpi_8_int is set and the gpi 8 interrupt condition is met. 0 gpi_7_int_en read/wr ite 0 = gpi_7_int is disabled. 1 = gpi_7_int enabled. asserts the gpi_int bit (register 0x01, bit 1) if gpi_7_int is set and the gpi 7 interrupt condition is met.
adp5585 data sheet rev. c | page 28 of 40 debounce_dis_a register 0x21 table 41 . debounce_dis_a bit descri ptions bit(s) bit name access description 7 to 6 n/a reserved . 5 gpi_6_deb_dis read/write (reserved except for adp5585ac_z -01- r7 options) 0 = debounce enabled on gpi 6. 1 = debounce disabled on gpi 6. 4 gpi_5_deb_dis read/write 0 = debounce ena bled on gpi 5. 1 = debounce disabled on gpi 5. 3 gpi_4_deb_dis read/write 0 = debounce enabled on gpi 4. 1 = debounce disabled on gpi 4. 2 gpi_3_deb_dis read/write 0 = debounce enabled on gpi 3. 1 = debounce disabled on gpi 3. 1 gpi_2_deb_di s read/write 0 = debounce enabled on gpi 2. 1 = debounce disabled on gpi 2. 0 gpi_1_deb_dis read/write 0 = debounce enabled on gpi 1. 1 = debounce disabled on gpi 1. debounce_dis_b register 0x22 table 42 . debounce_dis_b bi t descriptions bit(s) bit name access description 7 to 5 n/a reserved . 4 gpi_11_deb_dis read/write 0 = debounce enabled on gpi 11. 1 = debounce disabled on gpi 11. 3 gpi_10_deb_dis read/write 0 = debounce enabled on gpi 10. 1 = debounce disable d on gpi 10. 2 gpi_9_deb_dis read/write 0 = debounce enabled on gpi 9. 1 = debounce disabled on gpi 9. 1 gpi_8_deb_dis read/write 0 = debounce enabled on gpi 8. 1 = debounce disabled on gpi 8. 0 gpi_7_deb_dis read/write 0 = debounce enabled on g pi 7. 1 = debounce disabled on gpi 7. gpo_data_out_a register 0x23 table 43 . gpo_data_out_a bit descriptions bit(s) bit name access description 7 to 6 n/a reserved . 5 gpo_6_ data read/write (reserved except for adp5585ac_z -01- r7 options) 0 = sets output low. 1 = sets output high. 4 gpo_5_ data read/write 0 = sets output low. 1 = sets output high. 3 gpo_4_data read/write 0 = sets output low. 1 = sets output high. 2 gpo_3_ data read/write 0 = sets output low. 1 = sets output high. 1 gpo_2_ data read/write 0 = sets output low. 1 = sets output high. 0 gpo_1_data read/write 0 = sets output low. 1 = sets output high.
data sheet adp5585 rev. c | page 29 of 40 gpo_data_out_b register 0x24 table 44 . gpo_data_out_b bit descr iptions bit(s) bit name access description 7 to 5 n/a reserved . 4 gpo_11_ data read/write 0 = sets output low. 1 = sets output high. 3 gpo_10_ data read/write 0 = sets output l ow. 1 = sets output high. 2 gpo_9_ data read/write 0 = sets output low . 1 = sets output high. 1 gpo_8_ data read/write 0 = sets output low. 1 = sets output high. 0 gpo_7_data read/write 0 = sets output low. 1 = sets output high. gpo_out_mode_a register 0x25 table 45 . register 0x25, gpo_o ut_mode_a bit descriptions bit(s) bit name access description 7 to 6 n/a reserved . 5 gpo_6_out_mode read/write (reserved except for adp5585ac_z -01- r7 options) 0 = push/pull. 1 = open drain. 4 gpo_5_out_mode read/write 0 = push/pull. 1 = ope n drain. 3 gpo_4_out_mode read/write 0 = push/pull. 1 = open drain. 2 gpo_3_ out_mode read/write 0 = push/pull. 1 = open drain. 1 gpo_2_out_mode read/write 0 = push/pull. 1 = open drain. 0 gpo_1_out_mode read/write 0 = push/pull. 1 = op en drain. gpo_out_mode_b register 0x26 table 46 . register 0x26, gpo_out_mode_b bit descriptions bit(s) bit name access description 7 to 5 n/a reserved . 4 gpo_11_out_mode read/write 0 = push/pull. 1 = open drain. 3 gpo_10_ou t_mode read/write 0 = push/pull. 1 = open drain. 2 gpo_9_out_mode read/write 0 = push/pull. 1 = open drain. 1 gpo_8_out_mode read/write 0 = push/pull. 1 = open drain. 0 gpo_7_out_mode read/write 0 = push/pull. 1 = open drain.
adp5585 data sheet rev. c | page 30 of 40 gpio_direc tion_a register 0x27 table 47 . gpio_direction_a bit descriptions bit(s) bit name access description 7 to 6 n/a reserved . 5 gpio_6_dir read/write (reserved except for adp5585ac_z -01- r7 options) 0 = gpio 6 is an input. 1 = gpio 6 is an output. 4 gpio_5_dir read/write 0 = gpio 5 is an input. 1 = gpio 5 is an output. 3 gpio_4_dir read/write 0 = gpio 4 is an input. 1 = gpio 4 is an output. 2 gpio_3_dir read/write 0 = gpio 3 is an input. 1 = gpio 3 is an output. 1 gpio_2_dir read/write 0 = gpio 2 is an input. 1 = gpio 2 is an output. 0 gpio_1_dir read/write 0 = gpio 1 is an input. 1 = gpio 1 is an output. gpio_direction_b register 0x28 table 48 . register 0x28, gpio_direction_b bit descriptions bit(s) bit name access description 7 to 5 n/a reserved . 4 gpio_11_dir read/write 0 = gpio 11 is an input. 1 = gpio 11 is an output. 3 gpio_10_dir read/write 0 = gpio 10 is an input. 1 = gpio 10 is an output. 2 gpio_9_dir read/wri te 0 = gpio 9 is an input. 1 = gpio 9 is an output. 1 gpio_8_dir read/write 0 = gpio 8 is an input. 1 = gpio 8 is an output. 0 gpio_7_dir read/write 0 = gpio 7 is an input. 1 = gpio 7 is an output. reset1_event_a register 0x29 table 49 . reset1_event_a bit descriptions bit(s) bit name access description 7 reset1_event_a_level read/write defines which level the first reset event should be to generate the reset1 signal. for key events, use the following settings: 0 = not applicable; releases not used for reset generation. 1 = press is used as reset event. for gpis and logic outputs configured for fifo updates, use the following settings: 0 = inactive event used as reset condition. 1 = active event used as reset condition. 6 to 0 reset1_event_a[6:0] read/write defines an event that can be used to generate the reset1 signal. up to three events can be defined for generating the reset1 signal, using reset1_event_a[6:0], reset1_event_b[6:0], and reset1_ event_c[6:0]. if one of the registers is 0, that register is not used for reset generation. all reset events must be detected at the same time to trigger the reset.
data sheet adp5585 rev. c | page 31 of 40 reset1_event_b register 0x2a table 50 . reset1_event_b bit descript ions bit(s) bit name access description 7 reset1_event_b_level read/write defines which level the second reset event should be to generate the reset1 signal. refer to table 49. 6 to 0 reset1_event_b[6:0] read/wri te defines an event that can be used to generate the reset1 signal. refer to table 11. reset1_event_c register 0x2b table 51 . reset1_event_c bit descriptions bit(s) bit name access descript ion 7 reset1_event_c_level read/write defines which level the second reset event should be to generate the reset1 signal. refer to table 49. 6 to 0 reset1_event_c[6:0] read/write defines an event that can be used to generate the reset1 signal. refer to table 11 . reset2_event_a register 0x2c table 52 . reset2_event_a bit descriptions bit(s) bit name access description 7 reset2_event_a_level read/wri te defines which level the first reset event should be to generate the reset2 signal. for key events, use the following settings: 0 = not applicable; releases not used for reset generation. 1 = press is used as reset event. for gpis and log ic outputs configured for fifo updates, use the following settings: 0 = inactive event used as reset condition. 1 = active event used as reset condition. 6 to 0 reset2_event_a[6:0] read/write defines an event that can be used to generate the reset 2 signal. up to two events can be defined for generating the reset2 signal, using reset2_event_a[6:0], and reset2_event_b[6:0]. if one of the registers is 0, that register is not used for reset generation. all reset events must be detected at the same time to trigger the reset. reset2_event_b register 0x2d table 53 . reset2_event_b bit descriptions bit(s) bit name access description 7 reset2_event_b_level read/write defines which level the second reset event should be to generate the reset2 signal. refer to table 52. 6 to 0 reset2_event_b[6:0] read/write defines an event that can be used to generate the reset2 signal. refer to table 11. reset_cfg register 0x2e table 54 . reset_cfg bit descriptions bit(s) bit name access description 7 reset2_pol read/write sets the polarity of reset2. 0 = reset2 is active low. 1 = reset2 is active high. 6 reset1_pol read/write sets the polarity of reset1. 0 = reset1 is active low. 1 = reset1 is active high. 5 rst _passthru_en read/write allows the rst pin to override (or with) the reset1signal. this f unction not applicable to res et2.
adp5585 data sheet rev. c | page 32 of 40 bit(s) bit name access description 4 to 2 reset_trig_time[2:0] read/write defines the length of time that the reset events must be active before a reset signal is generated. all events must be active at the same time for the same duration. reset_trig_time[2:0] is common to both reset1 and reset2. 000 = immediate. 001 = 1.0 sec. 010 = 1.5 sec. 011 = 2.0 sec. 100 = 2.5 sec. 101 = 3.0 sec. 110 = 3.5 sec. 111 = 4.0 sec. 1 to 0 reset_pulse_width[1:0] read/write defines the pulse width of the reset signals. r eset_pulse_width[1:0] is common to both reset1 and reset2. 00 = 500 s. 01 = 1 ms. 10 = 2 ms. 11 = 10 ms. pwm_offt_low register 0x2 f table 55 . register 0x2f, pwm_offt_low bit descriptions bit(s) bit name access de scription 7 to 0 pwm_offt_low_byte[7:0] read/write lower eight bits of pwm off time. pwm_offt_high register 0x30 table 56 . pwm_offt_high bit descriptions bit(s) bit name access description 7 to 0 pwm_offt_high_byte[7:0] read/wr ite upper eight bits of pwm off time. pwm_o n t_low register 0x 31 table 57 . pwm_ont_low bit descriptions bit(s) bit name access description 7 to 0 pwm_ont_low_byte[7:0] read/write lower eight bits of pwm on time. pwm_o n t_ high reg ister 0x 32 table 58 . pwm_ont_high bit descriptions bit(s) bit name access description 7 to 0 pwm_ont_high_byte[7:0] read/write upper eight bits of pwm on time. note that updated pwm times are not latched until this byte is written to. pwm count times are referenced from the internal oscillator. the fastest oscillator setting is 500 khz (2 s increments). therefore, the maximum period is 2 s 2 16 = 131 ms this gives pwm frequencies from 500 khz down to 7.6 hz. pwm_cfg register 0x33 table 59 . pwm_cfg bit descriptions bit(s) bit name access description 7 to 3 n/a reserved . 2 pwm_in_and 0 = no external and ing. 1 = pwm signal and ed with an externally supplied pwm signal (c3). 1 pwm_mode read/write defines pwm mode. 0 = continuous. 1 = executes one pwm period, then sets pwm_en to 0. 0 pwm_en read/write enable pwm generator.
data sheet adp5585 rev. c | page 33 of 40 logic_cfg register 0x34 table 60 . logic_cfg bit descriptions bit(s) bit name access descript ion 7 n/a reserved . 6 ly_inv read/write 0 = ly output not inverted before passing into logic block. 1 = inverts output ly from the logic block. 5 lc_inv read/write 0 = lc input not inverted before passing into the logic block. 1 = inverts input lc before passing it into the logic block. 4 lb_inv r/w 0 = lb input not inverted before passing into the logic block. 1 = inverts input lb before passing it into the logic block. 3 la_inv r/w 0 = la input not inverted before passing into the logic block. 1 = inverts input la before passing it into the logic block. 2 to 0 logic_sel[2:0] r/w configures the digital mux for the logic block. refer to figure 19. 000 = off/disable. 001 = and. 010 = or. 011 = xor. 100 = ff. 101 = in_la. 110 = in_lb. 111 = in_lc. logic_ff_cfg register 0x35 table 61 . logic_ff_cfg bit descriptions bit(s) bit name access description 7 to 2 n/a read/write reserved . 1 ff_set read/write 0 = ff not set in the logic block. refer to figure 19. 1 = set ff in the logic block. 0 ff_clr read/write 0 = ff not cleared in the logic block. refer to fig ure 19. 1 = clear ff in the logic block. logic_int_event_en register 0x36 table 62 . logic_int_event_en bit descriptions bit(s) bit name access description 7 to 3 n/a reserved . 2 ly_dbnc_dis read/write 0 = output of the logi c block is debounced before entering the event/interrupt block. 1 = output of the logic block is not debounced before entering the event/interrupt block. use with caution because glitches may generate interrupts prematurely. 1 logic_event_en read/writ e 0 = ly cannot generate interrupt. 1 = allow ly activity to generate events on the fifo. 0 logic_int_level read/write configure the logic level of ly that generates an interrupt. 0 = ly is active low. 1 = ly is active high.
adp5585 data sheet rev. c | page 34 of 40 poll_time_cfg reg ister 0x37 table 63 . register 0x37, poll_time_cfg bit descriptions bit(s) bit name access description 7 to 2 n/a reserved . 1 to 0 key_poll_time[1:0] read/write configure time between consecutive scan cycles. 00 = 10 ms. 01 = 20 ms. 10 = 30 ms. 11 = 40 ms. pin_config_a register 0x38 table 64 . pin_config_a bit descriptions bit(s) bit name access description 7 to 6 n/a reserved. 5 r5_config read/write reserved except for adp5585ac_z -01-r7 options) 0 = gpio 6. 1 = row 5. 4 r4_config read/write 0 = gpio 5 (see r4_extend_cfg in table 66 for alternate configuration, reset1). 1 = row 4 3 r3_config read/write 0 = gpio 4 (see r3_extend_cfg[1 :0] in table 66 for alternate configuration, lc/pwm_out). 1 = row 3 2 r2_config read/write 0 = gpio 3 1 = row 2 1 r1_config read/write 0 = gpio 2 1 = row 1 0 r0_config read/write 0 = gpio 1/ly ( see r 0_extend_cfg in table 66 for alternate configuration, ly). 1 = row 0 pin_config_b register 0x39 table 65 . pin_config_b bit descriptions bit(s) bit name access description 7 to 5 n/a r eserved . 4 c4_config read/write 0 = gpio 11 (see c4_extend_cfg in table 66 for alternate configuration, reset2). 1 = column 4. 3 c3_config read/write 0 = gpio 10 . 1 = column 3. 2 c2_config read/write 0 = gpio 9 . 1 = column 2. 1 c1_config read/write 0 = gpio 8 . 1 = column 1. 0 c0_config read/write 0 = gpio 7 . 1 = column 0. pin_config_ c register 0x3a table 66 . pin_config_d bit descriptions bit(s) bit name access description 7 pull_select read/write 0 = 300 k ? resistor used for row pull - up during key scanning. 1 = 100 k? resistor used for row pull - up during key scanning. 6 c4_ extend_cfg read/write 0 = c4 remains configured as gpio 11. 1 = c4 reconfigured as reset2 output.
data sheet adp5585 rev. c | page 35 of 40 bit(s) bit name access description 5 r4_ extend_cfg read/write 0 = r4 remains configured as gpio 5. 1 = r4 reconfigured as reset1 output. 4 n/a reserved . 3 to 2 r3_extend_cfg[1:0] read/write 00 = r3 remains configured as gpio 4. 01 = r3 reconfigured as lc inpu t for the logic block. 10 = r3 reconfigured as pwm_out output from pwm block. 11 = unused. 1 n/a reserved . 0 r0_ extend_cfg read/write 0 = r0 remains configured as gpio 1. 1 = r0 reconfigured as ly output from the logic block. general_cfg r egister 0x3b table 67 . general_cfg bit descriptions bit(s) bit name access description 7 osc_en read/write 0 = disable internal 1 mhz oscillator. 1 = enable internal 1 mhz oscillator. 6 to 5 osc_freq[1:0] read/write sets the input clock frequency fed from the base 1 mhz oscillator to the digital core. slower frequencies result in less quiescent current, but key and gpi scan times increase. 00 = 50 khz. 01 = 100 khz. 10 = 200 khz. 11 = 500 khz. 4 to 2 n/a res erved . 1 int _cfg read/write configure the behavior of the int pin if the user tries to clear it while an interrupt is pending. 0 = int pin remains asserted if an interrupt is pending . 1 = int pin deasserts for 50 s and reasserts if an interrupt is pending. 0 rst _cfg r/w configure the response adp5585 has to the rst pin. 0 = adp5585 resets if rst is low. 1 = adp5585 does not reset if rst is low. int_en register 0x3c table 68 . int_en bit descriptions bit(s) bit name access description 7 to 5 n/a reserved . 4 logic_ien read/write 0 = logic 1 interrupt is disabled. 1 = assert the int pin if logic_int is set. 3 n/a reserved . 2 ovrflow_ien read/write 0 = overflow interrupt is disabled. 1 = assert the int pin if ovrflow_int is set. 1 gpi_ien read/write 0 = gpi interrupt is disabled. 1 = assert the int pin if gpi_int is set. 0 event_ien read/write 0 = event interrupt is disabled. 1 = assert the int pin if event_int is set.
adp5585 data sheet rev. c | page 36 of 40 applic ation s diagram sd a sc l r st i n t l ogi c p w m o s c i l l a t o r r e gi s t e r s v d d g n d h o s t p r o c ess o r k p / l ogi c 1 o u t p u t /g p i/g po k p / l ogi c 1 i n p u t /g p i/g po k p / l ogi c 1 i n p u t /g p i/g po k p / l ogi c 1 i n p u t /g p i/g p o/ p w m / c l k k p / r ese t 1 o u t p u t /g p i/g po sd a sc l r st i n t v d d v d d r 2 r 1 r 0 r 4 r 3 c 4 c 3 c 2 c 1 c 0 5 4 3 2 1 1 0 9 8 7 6 1 5 1 4 1 3 1 2 1 1 2 0 1 9 1 8 1 7 1 6 2 5 2 4 2 3 2 2 2 1 09841 - 02 6 ad p 558 5 g p i s ca n an d d e c o d e r ese t 1 g en r ese t 2 g en k e y s ca n an d d e c o d e u v l o p o r i 2 c i n t er f ac e i/ o c o n f i g figure 27 . typical application schematic
data sheet adp5585 rev. c | page 37 of 40 outline dimensions 10-23-2012- a a b c d 0.545 0.500 0.455 side view 0.230 0.200 0.170 0.300 0.260 0.220 coplanarity 0.05 sea ting plane 1 2 3 4 bot t om view (bal l side up) t op view (bal l side down) bal l a1 identifier 0.40 ref 1.20 ref 1.630 1.590 sq 1.550 figure 28 . 16 - ball wafer level chip scale package [wlcsp] (cb - 16 - 10) dimensions shown in millimeters 3.10 3.00 sq 2.90 0.30 0.23 0.18 1.75 1.60 sq 1.45 08-16-2010-e 1 0.50 bsc bot t om view top view 16 5 8 9 12 13 4 exposed pa d pin 1 indic a t or 0.50 0.40 0.30 se a ting plane 0.05 max 0.02 nom 0.20 ref 0.25 min coplanarity 0.08 pin 1 indic a t or for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 0.80 0.75 0.70 compliant to jedec standards mo-220-weed-6. figure 29 . 16 - lead lead frame chip scale package [lfcsp_wq] 3 x 3 mm body, very very thin quad (cp - 16 - 22) dimensions shown in millimeters
adp5585 data sheet rev. c | page 38 of 40 ordering guide model 1 temperature range package description package option branding adp5585acbz - 00- r7 ?40c t o +85c 16- ball wafer level chip scale package [wlcsp] cb - 16- 10 adp5585acbz - 01- r7 ?40c to +85c 16- ball wafer level chip scale package [wlcsp] cb - 16- 10 adp5585acbz - 02- r7 ?40c to +85c 16- ball wafer level chip scale package [wlcsp] cb - 16- 10 adp5585a cbz - 04- r7 ?40c to +85c 16- ball wafer level chip scale package [wlcsp] cb - 16- 10 adp5585acpz - 00- r7 ?40c to +85c 16- lead lead frame chip scale package [lfcsp_wq] cp - 16- 22 ljm adp5585acpz - 01- r7 ?40c to +85c 16- lead lead frame chip scale package [lfcsp _wq] cp - 16- 22 ljn adp5585acpz - 03- r7 ?40c to +85c 16- lead lead frame chip scale package [lfcsp_wq] cp - 16- 22 ljp adp5585cp - evalz lfcsp evaluation board cp - 16- 22 1 z = rohs compliant part.
data sheet adp5585 rev. c | page 39 of 40 notes
adp5585 data sheet rev. c | page 40 of 40 notes i 2 c refers to a communications protocol o riginally developed by philips semiconductors (now nxp semiconductors). ? 2011 C 2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners . d09841 - 0 - 1/13(c)

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